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-- Company: 
-- Engineer:
--
-- Create Date:   22:53:00 01/26/2014
-- Design Name:   
-- Module Name:   E:/XProject/Adder_test1/adder_testbench.vhd
-- Project Name:  Adder_test1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: adder
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY adder_testbench IS
END adder_testbench;

ARCHITECTURE behavior OF adder_testbench IS 

	-- Component Declaration for the Unit Under Test (UUT)

	COMPONENT adder
	PORT(
		 A : IN  std_logic;
		 B : IN  std_logic;
		 C : OUT  std_logic
		);
	END COMPONENT;
	

   --Inputs
   signal A : std_logic := '0';
   signal B : std_logic := '0';

  --Outputs
   signal C : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 

   constant <clock>_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: adder PORT MAP (
		  A => A,
		  B => B,
		  C => C
		);
  
   -- Clock process definitions
   <clock>_process :process
   begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin 
	  -- hold reset state for 100 ns.
	  wait for 100 ns; 

	  wait for <clock>_period*10;

	  -- insert stimulus here 

	  wait;
   end process;

END;